IS61DDP2B21M18A2 sram equivalent, 18mb ddr-iip (burst 2) cio synchronous sram.
DESCRIPTION
* 512Kx36 and 1Mx18 configuration available.
* On-chip Delay-Locked Loop (DLL) for wide data valid window.
* Common I/O read and write ports.
where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system o.
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